A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and Its Application to a 2-GHz RF Downconversion Mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2-V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500-mVP-P at both multiplier inputs. The 3-dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m single-poly-doublemetal N-well CMOS technology. The experimental results have shown that, under 3-V supply voltage and 2-dBm LO power, the mixer has 1-dB conversion gain, 2.2-GHz input bandwidth, 180MHz output bandwidth, and 22-dB noise figure. Under the LO frequency 1.9 GHz and the total dc current 21 mA, the thirdorder input intercept point is +7.5 dBm and the input 1-dB compression point is 9 dBm.